The present invention relates generally to an audio signal processor, and, more particularly, to an audio signal processor having a plurality of sub-processing units which are only driven when currently needed for processing.
A conventional audio processor or signal processor digitally processes an application program by using a signal processing unit, which leads the whole signal processing unit to be driven at every flow, causing power consumption of the processor to be very high. Especially, when a high performance program is processed at a high frequency, unessential parts of the hardware are driven, and more power is consumed.
According to a preferred embodiment of the invention, a low power audio processor is provided that comprises: a bit stream processing unit for bit processing an applied audio stream into a bit processed audio stream, and for decoding the bit processed audio stream to have a format conducive to digital signal processing. A digital signal processing unit is also included for digital signal processing the decoded bit processed audio stream from the bit stream processing unit to develop a digital signal processed audio stream. The audio processor further includes a post processing unit for receiving the digital signal processed audio stream from the digital signal processing unit to develop final audio data. A host interface unit is included for interfacing with an external device to provide an audio parallel stream received from the external device to the bit stream processing unit. A power control unit is included for determining the power state for each of the bit stream processing unit, the digital signal processing unit, and the post processing unit in response to (1) a request signal and an acknowledge signal between the digital signal processing unit and the post processing unit, (2) a power down signal and (3) a source clock, the power control unit outputting a determined power state as a power mode signal. There is also an internal clock signal generator unit for generating clock signals in response to the power mode signal, each of the clock signals corresponding to a respective one of the bit stream processing unit, the digital signal processing unit, and the post processing unit.